1. Field of the Invention
The invention is directed to the field of fabricating and manufacturing electronic devices. More specifically, the invention is directed to a measurement and detection method and apparatus for detecting defects in the manufacture of an electronic device such as a semiconductor integrated circuit or a wafer composed of a plurality of integrated circuits.
2. Description of Related Art
In the semiconductor industry, there is a continuing movement towards higher integration, density and production yield, all without sacrificing throughput or processing speed. The making of today's integrated circuits (ICs) requires a complex series of fabrication, inspection and testing steps interweaved throughout the entire process to ensure the proper balance between throughput, processing speed and yield. The inspections and tests are designed to detect unwanted variations in the wafers produced, as well as in the equipment and masks used in the fabrication processes. One small defect in either the devices produced or the process itself can render a finished device inoperable.
Many of the inspection steps once done manually by skilled operators have been automated. Automated systems increase the process efficiency and reliability as the machines performing the inspection are more consistent than human operators who vary in ability and experience and are subject to fatigue when performing repetitive tasks. The automated systems also provide greater amounts of data regarding the production and equipment, which enables process engineers to both better analyze and control the process.
One such automated inspection step is known as "pattern inspection." Many different "patterns" appear on both the wafer and the masks used to produce the ICs. Patterns may be repeated areas on a single IC such as test areas, memory areas, shift registers, adders, etc., or, as shown in FIG. 1, the ICs (or dies) themselves may be considered a "pattern" that is repeated throughout the wafer.
Typical pattern inspection systems are image based, as described, for example, in U.S. Pat. Nos. 4,794,646; 5,057,689; 5,641,960; and 5,659,172. In U.S. Pat. No. 4,794,646, for example, the wafer, or part thereof, is scanned and a highly resolved picture or image of the pertinent "pattern" is obtained. This pattern image is compared to other pattern images retrieved from the same or other wafers, or is compared to an ideal image stored in the inspection system database. Differences highlighted in this comparison identify possible defects in the IC or wafer.
Another inspection step that is typically automated in processes today is known as "critical dimension (CD) measurement." On each integration level there is a region or set of patterns or features whose dimensions are critical to the functioning of the entire circuit. A representative pattern is chosen for CD measurements. Examples of CD features include transistor channel length (gate length), transistor channel width, trench depth, step slope, spacing, contact dimensions, etc. Like pattern inspection, CD measurement can be done during several different stages in the fabrication process (e.g., masking, developing, final inspection, etc.).
With the increase in integration, the dimensions to be measured as CDs are so minute that scanning electron microscopes (SEMs) have replaced other optical systems as the tool for performing CD measurements. See, e.g., U.S. Pat. No. 5,109,430. Indeed, SEMs made exclusively for CD measurements are commonplace.
The ability of a viewing system to distinguish detail is related to the wavelength of the light (radiation) used. The shorter the wavelength, the smaller the detail that can be seen. With feature sizes breaking the sub-micron barrier, it is imperative that variations in the lower sub-micron range be detected. One error, even of this small magnitude, may be enough to render the entire IC or wafer useless. Only the SEM provides the capability to detect these variations.
For automated CD-SEMs, fiducial markers on wafers are typically included for the purpose of locating certain features or structures--usually test targets. U.S. Pat. No. 5,109,430, for example, discloses use of fine scale marks fabricated in a pattern in a two-dimensional array to form a target occupying a region of the IC where circuitry is not to be formed, e.g., between bonding pads or in a region interior to the bonding pads. Different patterns on different layers can be used to detect misalignment between layers, as well as measure critical dimensions of the patterns.
These "test targets" are specially designed structures included on the wafer for test purposes only. If the test targets are the correct size and shape, it follows that other semiconductor devices in their proximity will also have the correct size and shape and will therefore function properly. During its scanning of the wafer surface, the CD-SEM compares stored image data of the fiducial wafer markers with the scanned images received from the current position of the wafer under the CD-SEM. Once a "best match" is made, the CD-SEM is in correct position to perform the CD measurement on the intended "test target" for that particular location of the wafer (or IC).
With each new level of integration achieved, a number of new fabrication steps are introduced. This increase is inherently followed by a similar increase in the inspection and testing steps needed to ensure quality control of the products. The increased complexity of the process, however, typically leads to a reduction in throughput or processing speed.